1. Field of the Invention
The invention relates to computer systems having a clock signal which can operate at different speeds in different systems, and more particularly to a mechanism for detecting such clock frequency.
2. Description of Related Art
A typical personal computer systems includes a microprocessor, such as an Intel i386, i486 or Pentium.RTM. microprocessor, which is coupled to a CPU bus having data, address and control signal lines. The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases a timer, a real-time clock, and a cache memory. The typical IBM PC AT-compatible computer also includes an I/O bus, also known as an AT-bus, which is separate and distinct from the CPU bus. The I/O bus usually conforms to one of two industry-established standards known as ISA (Industry Standard Architecture) and EISA (Extended ISA). The I/O bus is coupled to the CPU bus via an I/O interface chipset, and includes address, data and control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by executing a special I/O instruction. Such an I/O instruction generates memory access signals on the CPU bus, but also activates an M/IO# signal on the CPU bus to indicate that this is an access to the I/O address space. The I/O interface chipset recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the I/O bus, and if appropriate, returns results to the CPU over the CPU bus.
In practice, some I/O addresses may reside physically on the CPU bus and some memory addresses may reside physically on the I/O bus. More specifically, the devices which respond to accesses to certain I/O space addresses may be connected to the control lines (and usually the address and data lines as well) of the CPU bus, while the devices which respond to accesses to certain memory space addresses may be connected to the control lines (and usually the address and data lines as well) of the I/O bus. The I/O interface circuitry is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "Technical Reference, Personal Computer AT" (1985), in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990), in MicroDesign Resources, "PC Chip Sets" (1992), and in Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including Intel Corp., "Pentium.TM. Processor", Preliminary Data Sheet (1993); Intel Corp., "Pentium.TM. Processor User's Manual" (1994); "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The various signals on the CPU bus include the input/output signals of whichever microprocessor the system is built around. Such signals are therefore well known in the industry and can be determined by reference to the above-incorporated publications. The various signals on the I/O bus also are well known in the industry. The Solari book incorporated above describes the lines in detail.
In an effort to minimize the number of integrated circuit chips required to build a PC AT-compatible computers, several manufacturers have developed "PC AT chipsets" (also known as "core logic chipsets" or "I/O bus interface chipsets"), which integrate a large amount of the I/O bus interface circuitry and other circuitry onto only a few chips. An example of such a chipset is the 386WB PC/AT chipset manufactured by OPTi Inc., Santa Clara, Calif. These chipsets implement the I/O bus interface circuitry, the timer, real-time clock (RTC), DMA controller, as well as some additional functionality.
For many purposes, the I/O interface chipset needs to know what the CPU clock frequency is. The CPU clock frequency is the frequency of a clock signal upon which all synchronous operations on the CPU bus are timed. The CPU clock speed can vary widely for different microprocessors. Presently, CPU clock speeds can vary from about 25 MHz to about 66 MHz. Note that as used herein, the CPU clock frequency is the frequency of the clock signal on the CPU bus. This clock signal is applied to the CPU itself, and it may be doubled, tripled or quadrupled internally to the CPU.
One reason that the CPU clock frequency needs to be known is that in typical systems, the I/O interface chipset generates the I/O bus BCLK signal by dividing down the CPU bus clock signal. The ISA specification requires that BCLK be between 6 MHz and 8.33 MHz, and marketing considerations mandate that it be as close to 8.33 MHz as possible. The chipset therefore needs to know the CPU clock frequency in order to know what divisor to use to generate BCLK.
As another example, for certain lengthy combinational signal paths in the system, if the I/O interface chipset needs to sample the output of the signal path synchronously with the CPU clock, then the chipset needs to know how many CPU clock signals to wait before sampling the result. For optimum performance, this number of clock cycles will depend on the frequency of the CPU clock signal.
In the past, the CPU clock frequency was determined through a software technique at system boot time. Specifically, the ROM firmware contained code which performed 1000 loops in RAM. Each iteration of the loop took a known number of CPU cycles, for example 100 CPU cycles, because the number of CPU cycles required for each instruction in the loop was known. Before starting the loop, an internal counter/timer was initialized. When the 1000 loops completed, the counter/timer was read. Since the input clock to the counter/timer was known to be approximately 1.19 MHz, the autodetect software was able to calculate the internal CPU speed by dividing the total number of CPU cycles executed in the loop (e.g. 100,000), by the time in seconds read from the counter/timer. This division was performed by a software table look-up.
Once the internal CPU clock speed was known, the software routine would read the CPU revision ID. This ID was used, together with a knowledge of the particular platform hardware, to calculate the CPU clock frequency external to the chip. For example, if the microprocessor was a DX2 chip and the iterative procedure calculated an internal clock frequency of 66.67 MHz, then the software determined that the external CPU clock frequency was half of 66.67 MHz, or 33.33 MHz. The software would then program I/O registers in the I/O interface chipset according to the detected clock speed.
The use of the software routine for detecting the CPU clock speed causes a number of problems. First, it takes a certain amount of time to complete, time which it would be preferable to avoid. Second, while the timing loop itself may be small, a certain amount of code was required to place the system in a known state to ensure that each iteration of the loop did in fact take the number of internal CPU clock cycles expected. For example, caching must be enabled to ensure that all instructions in the loop were fetched with the timing of a cache read hit.
Most significantly, however, the software detection mechanism must be tuned differently for different platforms. For example, different systems have different caching configurations and may require adjustments for that reason. As another example, different ones of the Intel microprocessors, and especially different Intel-compatible microprocessors which are not manufactured by Intel, may take a different number of internal CPU clock cycles to perform the different instructions in the loop. As yet another example, personal computers which are built around RISC-based microprocessors are becoming increasingly popular. These microprocessors do not necessarily support even the same instructions as those used in the auto-clock detect loop for an Intel microprocessor. Such systems also may not even include a counter/timer, and if they do, they may not be clocked at the 1.19 MHz frequency at which the Intel counter/timers are clocked. It has been suggested that clock frequency detection apparatus be included in hardware circuitry in the I/O interface chipset, but no mechanism for performing such detection or for communicating the detected frequency to the CPU, has been proposed.
Accordingly, there is a need for a mechanism for automatically detecting the frequency of a clock signal in a computer system without relying on a software timing loop.